Arista Networks (Co-op)

Dates: May 2013 to August 2013arista circuit board photo
Location: Santa Clara, California
Position: Hardware Engineering

At Arista, I was a member of about 30 or so hardware engineers designing the circuit boards powering their network switches. Being an intern, I wasn’t able to design production boards that went to customers. However I was given the opportunity to design a test board (see picture on the right) for a switch controller board, which would be used in the factories to ensure the controller boards manufactured by Arista functioned correctly.

Being the sole designer of the board, I was able to take the design from beginning to end, including the following stages of the design:

  1. Functional spec creation: Defined the hardware architecture of the board, as well as the registers used in the onboard Xilinx FPGA and Altera CPLD.
  2. Schematic entry: Created board level schematic in DxDesigner. Exported netlist and devices list in order to facilitate layout.
  3. Layout overview: guided and reviewed layout of components on the board before fabout and assembly of the test board.
  4. Verilog coding: leveraged and adapted existing Verilog code for the onboard FPGA and CPLD, allowing storage and manipulation of data in PLD registers by the Device Under Test (ie. the switch controller board)
  5. Bringup: debugged and reworked first batch of test boards delivered in order to make them functional. I had a particular issue with a twisted PCIe link that took me at least 4 days to fix. I also used this time to test and debug my verilog code.
  6. Board re-spin: After finding all mistakes and ensuring the test board worked, I updated my schematics to fix the circuit errors and sent them out for a final production run.

I should note here that before the work term I had no experience working with DxDesigner, and minimal experience in Verilog or HDL coding. In addition to learning Verilog and using DxDesigner I also had the opportunity to evaluate a few CPU core power supplies for a different project -in particular for their response to high current loads and imbalanced phase currents.